1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and method of manufacturing the same, and more particularly to a semiconductor integrated circuit device in which contact resistance between a bit line and a word line can be reduced and method of manufacturing the same.
2. Description of the Related Art
As semiconductor integrated circuit devices have progressed into high density integration and high speed performance, required design sizes of patterns formed in a chip have become smaller and spaces between interconnection lines have drastically decreased. Particularly, in a device such as a DRAM(dynamic random access memory) device, as the width of bit lines and word lines becomes narrower and the size of contacts becomes smaller, resistance in bit lines and word lines increases. Accordingly signal transfer delay(RC delay), cross talk (noise generating) and power consumption have become problems.
Therefore, research on architectural improvement and new material development to reduce interconnection resistance and manufacturing methods thereof have been performed. At present a polycide structure consisting of a polysilicon layer and a metal silicide layer thereon is widely applied to a bit line and a word line. The silicide has characteristics of {circle around (1)} low resistance like metal {circle around (2)} stability in high temperature {circle around (3)} easiness of pattern formation in a silicon layer or a polysilcon layer {circle around (4)} good mechanical stability such as good adherence and low stress {circle around (5)} no reaction with upper metal layer {circle around (6)} low contact resistance and low resistance susceptibility, and {circle around (7)} no contamination with wafer apparatus. Accordingly silicide is widely accepted as a new metalization material.
In a DRAM device, the polycide structure is first applied to bit lines. For word lines in a device using above half-submicron technology, strapping lines making a corresponding contact between a word line and a metal line are formed for reducing resistance in word lines. However, in a DRAM device using below half-submicron technology, a sub word-line drive structure is used to inhibit resistance increase in word lines instead because metal interconnection lines can not be formed narrow enough to form strapping lines. At present, a polycide structure is also applied to a word line to reduce resistance of the word line itself. However, a polycide word line structure applied in a highly integrated DRAM device reduces sheet resistance, but contact resistance between a word line and a bit line formed in peripheral circuit regions increases.
FIG. 1 and FIG. 2 are cross-sectional views for illustrating a conventional method for manufacturing a semiconductor integrated circuit device having a polycide word line and a polycide bit line.
Referring to FIG. 1, after forming a gate oxide(12) by thermal oxidation on a semiconductor substrate(10), in which an active region and a device isolation region are divided by a field oxide(11), an impurity (for example phosphorus) doped first polysilicon layer(14) and a first silicide layer(16) are formed consecutively thereon. Subsequently, patterning of the first silicide layer(16) and the first polysilicon layer(14) by a photo-etching method forms a polycide word line(18). Thereafter an insulating layer(20) on the entire surface including the polycide word line(18) and the field oxide(11) is formed. Subsequently, a contact hole(22) exposing the first silicide layer(16) of the word line(18) is formed by a photo-etching method.
Referring to FIG. 2, an impurity(for example phosphorus) doped second polysilicon layer(24) and a second silicide layer(26) are formed consecutively on the insulating layer(20) and the contact hole(22). Subsequently, a polycide bit line(28) connected electrically to the word line(18) is formed by patterning the second silicide layer(26) and the second polysilicon layer(24) by a photo-etching method.
In the conventional method as described above, impurity(for example phosphorus) doped in the second polysilicon layer (24)of the bit line positioned between the second silicide layer(26) of the bit line and the first silicide layer(16) of the word line, diffuse out to the adjacent silicide layer(the first silicide layer (16) of the word line) in a subsequent heat treatment (for example 800-1000xc2x0 C., N2 ambient, 30 minutes). In worse case conditions, the impurity diffuses out also to the first polysilicon layer (14) of the word line. Accordingly, impurity concentration in the second polysilicon layer (24) of the bit line is drastically reduced due to impurity redistribution as described above. As a result contact resistance between the bit line(28) and the word line(18) is increased.
To take care of this situation, an additional ion implantation after forming the contact between the bit line (28) and the word line(18) is performed. However this additional ion implantation makes cell isolation characteristics weak, because ions are injected also into cell array regions.
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device in which contact resistance between a first polycide layer and a second polycide layer can be reduced.
Another object of the present invention is to provide a semiconductor integrated circuit device in which contact resistance between a word line and a bit line can be reduced.
Still, another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device so as to reduce contact resistance between a word line and a bit line.
In an exemplary embodiment of the present invention, there is provided a semiconductor integrated circuit device comprising a first conductive line formed on a semiconductor substrate. An insulating layer formed on the first conductive line and the semiconductor substrate has a first contact hole exposing the first conductive line. A second conductive line consisting of a polysilicon layer and a silicide layer thereon is formed on the insulating layer including the first contact hole. The polysilicon layer of the second conductive line is formed extended from the sidewall of the first contact hole to the top of the insulating layer so as to expose the first conductive line. The silicide layer of the second conductive line is formed so that it is directly connected to the exposed first conductive line in the first contact hole.
In a preferred exemplary embodiment, the first conductive line preferably consists of a polysilicon layer and a silicide layer thereon. The polysilicon layer of the second conductive line is formed extended from the sidewall of the first contact hole to the top of the insulating layer so as to expose the silicide layer of the first conductive line. The silicide layer of the second conductive line is formed so that it is directly connected to the exposed silicide layer of the first conductive line.
In an alternate embodiment of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device. The method comprises forming a first conductive line on a semiconductor substrate; forming an insulation layer on the semiconductor substrate in which the first conductive line is formed; forming a first contact hole exposing the first conductive line by etching the insulating layer; forming a polysilicon layer of a second conductive line on the insulating layer including the first contact hole; exposing the first conductive line by removing the polysilicon layer of the second conductive line formed on the bottom area of the first contact hole by etching the polysilicon layer of the second conductive line; and connecting directly the exposed first conductive line to a silicide layer of the second conductive line by forming the silicide layer on the exposed first conductive line and the polysilicon layer of the second conductive line.